Variable Integer Rate Decimation Filter Design Example v9.1 README File This readme file contains the following sections: o Package Contents o Tool Requirements o General Description o Simulation in Simulink o References o Release History o Design Examples Disclaimer o Contacting Altera Package Contents ================ Altera Variable Rate Decimation Filter v9.1 Design Example Files in this zip download include: o vardecimator_rt.mdl - DSP Builder Advanced Blockset design file for variable rate decimation filter o setup_vardecimator_rt.m - MATLAB script to configure initialization and parameters of vardecimator_rt.mdl o stop_vardecimator_rt.m - MATLAB script to plot variable rate decimation filter output and compare it with input waveform o vardecimator_rt_bare.mdl - Design file based on vardecimator_rt.mdl. Some none-synthesizable test bench blocks are removed for RTL generation Tool Requirements ================= This design example requires the following software package: o Quartus II 9.1 o DSP Builder Advanced Blockset v9.1 o MATLAB/Simulink version R2009a (Design verified in R2009a; DSP Builder Advanced Blockset requires 2007a or later) Please contact your local sales representative if you do not have one of these software tools. General Description ============================= The variable rate decimation filter design example demonstrates how to use Altera DSP Builder Advanced Blockset (DSPB-AB) to implement a decimation filter that can change its decimation rate at run time. It also supports multiple channels and exploit automatic folding of DSPB-AB to generate RTL that maximizes hardware reuse for resource saving. The current design supports decimation rate 1, 2, 4, 8 and 16. However it can be easily modified to support other integer decimation rates. Decimation by M filters can be efficiently implemented via polyphase decomposition with an input commutator and M parallel paths. Each path is a polyphase of the original prototype filter. If the input commutator delivers successive samples to successive legs or phases of the M-path filter, it takes M cycles at input sample rate to cycle through all the phases and to generate one output. Consequently the output sample rate is 1/M of the input sample rate. If the input commutator skips every other phase, the output sample rate becomes 2/M, and so on. In the real design, instead of having a commutator and a parallel bank of FIR paths, we implement only one polyphase FIR, where the coefficients corresponding to the polyphases change every cycle at input sample rate. It has the same effect as delivering input samples successively to a parallel bank of polyphases. We store the polyphase coefficients in memory, and use an input accumulator like the one used in numerically controlled oscillator (NCO) to control which phase is currently being read out and sent to the FIR path. The step size of the phase accumulator controls how fast the system cycles through the polyphases hence the decimation rate. The overflow signal of the accumulator indicates when the phases have been cycled through. When it asserts, a valid output sample is generated at the lower sample rate. The FIR path is a modified direct form FIR filter. Suppose the prototype decimation filter has a total of M*L taps and is being decomposed into M polyphases. Each polyphase has L taps. The L coefficients are from the coefficients look up table (LUT) and change from one polyphase to another. An accumulator is attached to each of the multiplier output. It accumulates the outputs of all polyphases at its tap till the rollover signal indicates that all phases have been visited and an output is due. At that moment, a multiport adder adds up all L accumulator outputs and generates a final decimated sample. At the same time, the accumulators clear the contents and get ready to the next accumulating cycle. In this example, we implement the prototype filter as decimation by 16 with 160 taps in total. Thus each polyphase has 10 taps. Decimation rate of 1, 2, 4, 8 and 16 can be achieved by varying the step size of the accumulator to 16, 8, 4, 2 and 1 phases, respectively. Reconfiguration of decimation rate change is achieved by varying the accumulator phase increment or step size at run time. The phase increment can be updated real time by a processor via Avalon Memory Mapped interface. In this design, we use a BusStimulus block to mimic a processor interface, where we can update control registers and filter coefficient memories at run time. The phase transition of the implemented algorithm is continuous. In the provided setup script, we arbitrarily picked a time to change the decimation rate, thus you may see a sudden change of sample values at sample rate transition instant. If you plan your register update carefully taking into consideration the clock rate, sample rate and input data contents, you should be able to achieve a smooth transition. When the decimation rate changes, the number of polyphases accumulated in the FIR path also changes. To maximize dynamic range, we can supply a reconfigurable scaling factor to the multiply-and-accumulate units and to the final adder output. This control register can also be reconfigured via a processor through the Avalon Memory Mapped interface. Many of the design parameters, including FPGA clock rate, number of channels, bit width at various stages of the design can be fully parameterized in the setup script. Simulation in Simulink ====================== To run the functional simulation of the design example in Simulink, perform the following steps for 9.1 release: 1. Open the design file vardecimator_rt.mdl 2. Double click on the Control block on the top design, and uncheck 'Generate Hardware'. We will first do a functional simulation only to verify the algorithm and save on simulation time. We will turn on hardware generation later to generate synthesizable RTL, which takes longer in 9.1 In future release the compile time for generating RTL should be significantly shorter. 3. Double click the Editparam block in top level design and open the setup script setup_vardecimator_rt.m 4. Review or modify parameters used in the design example 5. To start simulation, select "Start" (Simulation menu) and run the simulation. Make sure the discrete solver is selected with variable simulation steps. Variable simulation step is required by the folding feature. 6. Check the simulation inputs and outputs. The input is a sinusoidal wave, and the output is a decimated sinusoidal wave depending on your choice of parameters. If multiple decimation rate and their cooresponding scaling factors are properly specified in the setup script, you could observe the sample rate change on the output signal in the top level Output Scope. Once you are satisfied with the functionality of the algorithm, you can turn on hardward generation in the Control block of vardecimator_rt_bare.mdl to generate synthesizable RTL and review resource utilization estimate before you start a Quartus II compilation of your design. The synthesizable part of the two design files are idential with vardecimator_rt_bare.mdl having some test bench only blocks removed. In future releases you will be able to compile directly vardecimator_rt.mdl. References ============== 1. Stephen et al, Methods and apparatus for variable-rate down-sampling filters for discrete-time sampled systems using a fixed sampling rate, US Patent 6014682, 2000. 2. Fredric J Harris, Multirate Signal Processing for Communication Systems, Prentice Hall, 2004. 3. DSP Builder Advanced Blockset User Guide http://www.altera.com/literature/ug/ug_dsp_builder_adv.pdf Release History =============== Version 9.1 ------------- Initial release Design Examples Disclaimer ========================== These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera. Contacting Altera ================= Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered. If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, please contact your Altera Field Applications Engineer. If you have additional questions that are not answered in the documentation provided with this function, please contact Altera Applications: World-Wide Web: http://www.altera.com http://www.altera.com/mysupport/ Technical Support Hotline: (800) 800-EPLD (U.S.) (408) 544-7000 (Internationally) Copyright (c) 2006 Altera Corporation. All rights reserved.