Basic Mode

Table 1. 3G/6G Basic Modes and PCS Blocks

Transceiver Feature

Stratix® V
GT, GX, GS FPGAs

Stratix® IV
GT, GX FPGAs

Stratix® II GX FPGAs

Arria® II
GX, GZ FPGAs

Arria® V
GX, GT FPGAs

Cyclone® IV GX FPGAs

Data Rates (Gbps)

0.6 to 8.5

0.6 to 8.5
(Stratix IV GT, Stratix IV GX)

0.6 to 6.375

0.6 to 6.375

0.6 to 10.375

0.6 to 3.125

Basic Mode Channel Bonding

Yes

Yes

No

Yes

Yes

Yes

Possible Reference Clock (MHz)

50.0 to 622.08

50.0 to 622.08

50.0 to 622.08

50.0 to 622.08

27 to 710

5.0 to 472.5

FPGA Bus Width (Bits)

8, 10, 16, 20, 32, 40

8, 10, 16, 20, 32, 40

8, 10, 16, 20, 32, 40

8, 10, 16, 20

8, 10, 16, 20, 32, 40, 80

8, 10, 16, 20

8B/10B Encode/Decode

Dedicated Synchronization State Machine

Word Align

Rate Match

Byte Serialize/ Deserialize

Phase Compensation FIFO

Dynamic Reconfiguration

Byte Ordering

Single Bit Slip

Table 2. 10G Basic Modes and PCS Blocks

Transceiver Feature

Stratix V GT, GX, and GS FPGAs

Stratix IV GT FPGAs

Data Rates (Gbps)

9.9 to 12.5

9.9 to 11.3

Basic Mode Channel Bonding

Yes

Yes

Possible Reference Clock (MHz)

50.0 to 622.08

50.0 to 622.08

FPGA Bus Width (Bits)

32, 40, 64

40

Word Align

Phase Compensation FIFO

Dynamic Reconfiguration

64B/66B Encode/Decode

-

Gearbox (Reduction/Expansion)

-

Block Synchronization

-

Receive Bit Slip

-

Transmit Bit Slip

-