F-Tile SDI II FPGA IP Design Example User Guide

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ID 710496
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Component
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description 2.4.3. Hardware Testing 2.4.4. Signal
2.4.3. Hardware Testing x
2.4.3.1. Parallel loopback 2.4.3.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide

2.4.1. Testbench Components

Figure 21. Simplex Mode Simulation Testbench Block Diagram
Note:
  • Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
  • (1)Block/Connection only required for triple rate/multi rate designs.
  • (2)Block/Connection only required for for Tx PLL reference clock switching designs.
Figure 22. Duplex Mode Simulation Testbench Block Diagram
Note:
  • Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
  • (1)Block/Connection only required for triple rate/multi rate designs.
  • (2)Block/Connection only required for for Tx PLL reference clock switching designs.
Table 11.  Testbench Components
Component Description
Testbench Control This block controls the test sequence of the simulation and generates the necessary stimulus signals to the TX and video pattern generator blocks.
TX checker This checker verifies if the TX serial data contains a valid TRS signal.
RX checker

This checker detects the trs_locked signal from the RX protocol and compares the actual number of transceiver reconfigurations performed versus the expected number.

Level Two Title