Portable handheld-size devices can implement mobile monitoring of patient vital signs, such as heart pacing, blood pressure, and glucose tracking.
These portable devices have been implemented using a host of discrete components and a CPU. It takes more time and resources to implement these custom hardware platforms, resulting in:
- Wasteful efforts developing standard blocks instead of custom application blocks
- Obsolescence risk from multiple discrete ASSP processor components
- Integration risk, cost, and inflexibility of ASICs
With the latest Intel Quartus Prime Design Software, Platform Designer, Nios® II embedded processor, SoC device family, and programmable hardware capabilities of Intel Cyclone®, Intel Arria® and Intel Stratix® FPGAs, you can:
- Integrate multiple ASSP devices and the processor into a single application-independent FPGA
- Implement independent functions into multiple Nios II processors on a single FPGA
- Generate coprocessing logic to “supercharge” functional performance
- Easily integrate all the application-specific and standard intellectual property (IP) blocks with Platform Designer
Additional productivity benefits include:
- Reusing previous internal engineering IP development efforts
- Leveraging additional Intel FPGA and partner IP blocks
- Separating application-specific analog I/O and sensor circuits onto modular daughter cards
The figure below shows how an Intel Cyclone or Intel Stratix series FPGA implements a system-on-a-programmable-chip solution using one of more Nios II processors, including custom logic. The user interface, application-specific analog functionality, and network connectivity can be added to complete the portable device.