Cyclone® V FPGAs Features
The Cyclone® V FPGA core architecture comprises the following:
- Up to 300K equivalent logic elements (LEs) arranged as vertical columns of adaptive logic modules (ALMs).
- Up to 12 Mb of embedded memory arranged as 10 Kb (M10K) blocks.
- Up to 1.7 Mb of distributed memory logic array blocks (MLABs).
- Up to 342 variable-precision digital signal processing (DSP) blocks that can implement up to 684 18x18 embedded multipliers.
- Eight fractional clock synthesis phase-locked loops (PLLs).
All of these logic resources are interconnected through a highly flexible clocking network, with over 30 global clock trees and a power-optimized version of Intel's high-performance MultiTrack routing architecture.
Flexible Interface Support
Cyclone® V FPGAs provide flexible interface support with up to 12 5-Gbps transceivers on the left side of the die. The logic and routing core fabric is surrounded by I/O elements and PLLs. Cyclone® V devices have two to eight PLLs. The I/O elements support 840 MHz LVDS and 800 Mbps of external memory bandwidth. These I/O elements provide support for all mainstream differential and single-ended I/O standards including 3.3 V LVTTL at up to 16-mA drive strength.
Abundant Hard IP
Cyclone® V FPGAs include hard intellectual property (IP) blocks, such as an ARM*-based HPS, up to two PCI Express* (PCIe*) hard IP blocks, and up to two hardened multiport memory controllers. The hardened PCIe block supports widths up to four lanes for Gen1 and four lanes for Gen2 applications, and now includes multifunction support. Multifunction support allows up to eight peripherals to share a single PCIe link with individual memory map and control and status registers (CSRs) to simplify software driver development. The hardened multiport memory controller can arbitrate between up to six different masters and offers command and data reordering to maximize the efficiency of your DRAM link.
To protect your valuable IP investments, Cyclone® V FPGAs also provide the most comprehensive design protection available in FPGAs, including 256 bit Advanced Encryption Standard (AES) bitstream encryption, JTAG port protection, internal oscillator, zeroization (active clear), and cyclic redundancy check (CRC) features.
The multiport memory controller IP supports the following features:
- User configurable timing parameters set during compilation or during FPGA operation.
- Support for up to 4 Gb memory device per chip select.
- Two chip selects.
- Configurable memory width of 8, 16, 24, 32, and 40 bits.
- Hard error correction code (ECC) support for 16-bit and 32 bit data widths.
- Flexible fabric interface port configuration with up to six command ports and up to 256 bits of data.
- Bonding of two controllers to service higher bandwidth applications by creating a virtual x64 memory.
- DRAM power savings, including auto-refresh and deep power down.
The multiport memory controller consists of two major blocks as shown in Multiport Memory Controller Architecture diagram :
- Multiport front end—handles the arbitration of memory reads and writes between up to six masters.
- PHY—interfaces between the memory controller and the memory devices. Performs the actual read and write operations to and from the external memory.
The multiport front end provides the following arbitration and reordering features:
- Command and data reordering to boost bus efficiency.
- Out-of-order execution of DRAM commands.
- Collision detection and in-order return of results.
- Dynamically configurable priority support with both absolute and relative priority scheduling.
The PHY interface on the multiport memory controller offers the following calibration features for data sequencing and timing control:
- Hardened read FIFO buffer in input register path.
- Dedicated DDR registers in the I/O elements.
- Dynamic deskew delays with 25 ps resolution to optimize the sampling window.
- Skew adjustment circuitry to allow full path calibration from FPGA logic to the memory device on both read and write paths.
- On-chip termination calibration to limit termination impedance variation.
- On-chip dynamic termination to swap between serial and parallel termination for optimal signal integrity.
- DLL delay chain for temperature-compensated DQS phase shifts.
The multiport memory controller hard IP in the Cyclone® V FPGA supports DDR3 SDRAM, DDR2 SDRAM, and LPDDR2 (single-rank support only). The Cyclone® V FPGA also supports the soft memory controllers for the memory interfaces mentioned.
Cyclone® V Power Consumption Compared to Previous-Generation FPGAs
Accurate Power Estimation and Analysis
Intel makes power estimation and analysis from design concept through implementation easy, with the most accurate and complete power management design tools in the industry. Intel offers the following power estimation and analysis resources:
- Early power estimators.
- Intel® Quartus® Prime Software power analysis and optimization technology.
- Power Management Resource Center.
When designing, you can use the early power estimator (EPE) during the design concept phase and the power analyzer during the design implementation phase. The EPE is a spreadsheet-based analysis tool that enables early power scoping based on device and package selection, operating conditions, and device utilization. The power models in the EPE are correlated to silicon, ensuring an accurate estimation of your design's power consumption.
The power analyzer is a far more detailed power analysis tool that uses actual design placement and routing, logic configuration, and simulated waveforms to estimate dynamic power very accurately. The power analyzer, in aggregate, provides approximately 10-percent accuracy when used with accurate design information. Intel® Quartus® Prime Software power models are correlated to silicon measurements based on over 5,000 test configurations per circuit.
Throughout the design process the Power Management Resource Center provides useful information regarding power, thermal management, and power supply management.
Intel® Quartus® Prime Software Optimization
Design implementation details can improve performance, minimize area, and reduce power. Historically, the performance and area tradeoffs have been automated within the register transfer level (RTL) through the place-and-route design flow. Intel has taken a leadership position in bringing power optimization into the design flow. Intel® Quartus® Prime Software optimization tools automatically use the Cyclone® V architecture capabilities to reduce power further, resulting in up to 10 percent lower total power consumption when enabled.
The Intel® Quartus® Prime Software optimization has many automatic power optimizations that are transparent to you but provide optimal utilization of FPGA architecture details to minimize power, including:
- Transforming major functional blocks.
- Mapping user RAM so they use less power.
- Restructuring logic to reduce dynamic power.
- Correctly selecting logic inputs to minimize capacitance on high-toggling nets.
- Reducing area and wiring demand for core logic to minimize dynamic power in routing.
- Modifying placement to reduce clocking power.
Cyclone® V SoC Hard Processor System
925 MHz, dual-core ARM* Cortex-A9 MPCore processor. Each processor core includes:
- 32 KB of L1 instruction cache, 32 KB of L1 data cache.
- Single- and double-precision floating-point unit and NEON* media engine.
- CoreSight* debug and trace technology.
- 512 KB of shared L2 cache.
- 64 KB of scratch RAM.
- Multiport SDRAM controller with support for DDR2, DDR3, and LPDDR2 and optional error correction code (ECC) support.
- 8-channel direct memory access (DMA) controller.
- QSPI flash controller.
- NAND flash controller with DMA.
- SD/SDIO/MMC controller with DMA.
- 2x 10/100/1000 Ethernet media access control (MAC) with DMA.
- 2x USB On-the-Go (OTG) controller with DMA.
- 4x I2C controller.
- 2x UART.
- 2x serial peripheral interface (SPI) master peripherals, 2x SPI slave peripherals.
- Up to 134 general-purpose I/O (GPIO).
- 7x general-purpose timers.
- 4x watchdog timers.
Cyclone® V GX FPGAs: Transceiver Overview
Not all low-cost transceivers are created equally. Intel's Cyclone® V FPGA family has a flexibility that helps you fully utilize all available transceiver resources and keep designs in a smaller and lower cost device. The Cyclone® V FPGAs provide the most flexibility in implementing independent protocols, implementing proprietary protocols with hardened building block, all at the lowest power possible.
By providing the market's lowest cost, lowest power FPGAs, Intel's Cyclone® V FPGA family extends the Cyclone® FPGA series. Intel's transceiver leadership is re-affirmed with actual shipment of working transceiver I/O within an FPGA design. Watch the video below to see Cyclone® V FPGAs in action.
The Cyclone® V FPGA series offers two variants to meet your design needs, the Cyclone® V GX FPGAs with transceivers up to 3.125 G and Cyclone® V GT FPGAs with transceivers up to 6.144 G.
Key Transceiver Features
- Up to twelve transceivers supporting data rates from 600 Mbps to 3.125 Gbps or 6.144 Gbps.
- Flexible and easy-to-configure transceiver datapath to implement industry-standard and proprietary protocols.
- Programmable pre-emphasis settings and adjustable differential output voltage (VOD) for improved signal integrity (SI).
- User-controlled receiver equalization to compensate for frequency-dependent losses in the physical medium.
- Dynamic reconfiguration of the transceiver to support multiple protocols and data rates on the same channel without reprogramming the FPGA.
- Support for protocol features such as spread-spectrum clocking in PCI Express* (PCIe*), Common Public Radio Interface (CPRI), DisplayPort, V-by-One, and SATA configurations.
- Dedicated circuitry compliant with the physical interface for PCIe* , XAUI, and Gbps Ethernet (GbE).
- PIPE interface that connects directly to embedded PCIe* Gen1 (2.5 Gbps) and Gen2 (5 Gbps) hard intellectual property (IP) to support PCI-SIG* compliant x1, x2, or x4 endpoint or root port applications.
- Built-in byte ordering so that a frame or packet always starts in a known byte lane.
- 8B/10B encoder and decoder that performs 8 bit to 10 bit encoding and 10 bit to 8 bit decoding.
- On-die power supply regulators for transmitter and receiver phase-locked loop (PLL) charge pump and voltage controlled oscillator (VCO) for superior noise immunity.
- On-chip power supply decoupling to satisfy transient current requirements at higher frequencies, which reduces the need for on-board decoupling capacitors.
- Diagnostic features such as serial loopback, parallel loopback, reverse serial loopback, and loopback master and slave capability in the PCI-SIG* compliant PCIe* hard IP block.
PCS block diagram shows the Cyclone® V FPGA transceivers, both physical medium attachment (PMA) and physical coding sublayer (PCS). The blocks within the PCS can be bypassed, depending on your requirements.
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