Intel® Quartus® Prime Software

The intuitive high-performance design environment.

Quick-Start for Intel® Quartus® Prime Pro Edition Software

Intel® Quartus® Prime Pro Edition User Guide: Getting Started

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Intel® Quartus® Prime Software

Intel® Agilex™ Device Support

The Intel® Quartus® Prime Pro Edition Software v22.2 supports the Intel® Agilex™ device family. Intel® Agilex™ FPGA devices leverage heterogeneous 3D system-in-package (SiP) technology to integrate Intel’s first FPGA fabric built on 10 nm SuperFin Technology. Leveraging this advanced process technology and 2nd Gen Intel® Hyperflex™ FPGA Architecture enables these FPGAs to deliver ~2X better fabric performance per watt1 when compared to our competition’s 7 nm FPGA portfolio. For applications requiring embedded processors, Intel® Agilex™ SoC FPGAs offer integrated quad-core Arm* Cortex-A53 processor.

Nios® V Processor

  • Added support for the reset request interface for the Nios® V processor intellectual property (IP).
  • Added new design examples in the Nios® V/m Processor Intel FPGA IP core parameter editor:
  • uC/TCP-IP IPerf Example Design
  • uC/TCP-IP Simple Socket Server Example Design
  • For more information, see the

Nios® V Processor Release Notes ›

Nios® V Processor Reference Manual ›

RiscFree* IDE for Intel FPGAs

  • New integrated development environment (IDE) for software development and debug on the Nios® V Processor.
  • Included with the Quartus Prime Pro Software version 22.2 onwards.
  • Available as a standalone free download for embedded software developers.
  • Full tool-chain including Ashling’s* RiscFree* for Intel FPGAs IDE, Compiler, Debugger and Trace.
  • IDE based on Eclipse with full source and project creation, editing, build and debug support.
  • And More.
  • For more information, see

RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide ›

RTL Analyzer and the Design Netlist Infrastructure (Beta)

Design Netlist Infrastructure

The Design Netlist Infrastructure (DNI) project provides the Intel Quartus Prime Pro Software with a unified database that has a well-understood and easy-to-use data model, an application interface with clean separation from the database layer, and finally a uniform and comprehensive scripting interface to this database. The first application built on top of the Design Netlist infrastructure is the RTL Analyzer.

DNI Synthesis Flow

  • Split Analysis & Elaboration and Synthesis
  • Users can see different stages of their designs side by side
  • Modular flow steps
  • Tcl access to design data

RTL Analyzer

  • WYSIWYG netlist viewer
  • Faster design loading
  • Optimization Hits
  • Visualize logic optimized out
  • Capable of handling over 10 million records
  • Fast filtering to focus on swept hierarchies
  • Unified cross probing across different design views
  • Connectivity Tracer enable user to explore logical connections in design

Design Assistant / Snapshot Viewer

The Design Assistant and Snapshot Viewer are productivity tools meant for novice and advanced users. These tools enable faster design closure by reducing the number of design iterations required and speed every iteration with targeted sanity checks and guidance at every stage of the compilation process. View the video to learn more about the Design Assistant and Snapshot Viewer.

In the Intel® Quartus® Prime Pro Edition Software v22.2, we have continued to add new rules as well as refining many of the existing rules to make it more useful for getting to timing closure faster.

  • Memory initialization DRCs
  • F-Tile and Dynamic Reconfiguration DRCs
  • New DRC linting rules to help avoid RAM corruption

Additionally, performance improvements have been made to the static timing analysis engine. Many of the Design Assistant rules support cross probing to timing reports to make it easier to investigate paths.

Introduction to Design Assistant

Get an overview of the new Design Assistant tool in the Intel® Quartus® Prime Pro Edition Software.

Timing Closure with Design Assistant

Design Assistant timing closure rules will help you find timing violations and get to closure faster.

Get More Out of Design Assistant

Learn how to filter and customize Design Assistant rules to fit your needs.

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New Reports

The Intel® Quartus® Prime Pro Edition Software continues to expand its rich set of compilation reports. In the v22.2 software release, the following new reports have been added:

  • Visualize global routing congestion
  • Unexpected clock crossings
  • Support-Logic Generation Report for F-Tile

In addition to the new and improved reports, cross-probing between reports is supported in many of them. This expanding portfolio of reports enables you to gather detailed information about routing, congestion, timing, tension, span, routing effort, and many other metrics that will provide rapid feedback for closing timing quickly.

Tile Interface Planner

The Intel® Quartus® Prime Tile Interface Planner is a new feature that helps you to quickly place component IP in legal tile locations of F-tile. Tile Interface Planner is an interactive floorplanning tool that simplifies legal placement of component IP on device tiles.

Tile Interface Planner displays your project component IP in a hierarchical tree view, next to a visual representation of the device tile segments. You can then locate the potential legal locations for each IP within the tile, place the IP at the location, and apply the placement constraints to the project for downstream Compiler stages.

New features available with the v22.2 version of the Tile Interface Planner include

  • Tile Assignment Editor
  • New GUI for entering dynamic reconfiguration intent with single and multi-rate IP
  • Create dynamic reconfiguration groups
  • Generates assignments and validation
  • New Reconfiguration Group pane
  • Visualization of every Reconfig group
  • Synchronized selection views
  • Review placement of Multi-rate IPs with different profiles
  • Visualize placement of DR group member IPs
  • Interactive placement
  • Multi-rate IP honoring relative constraints
  • User-defined DR groups

Using the Tile Interface Planner

The Tile Interface Planner allows you to physically place your F-Tile Intel IP in locations validated by the tool.

F-Tile Channel Placement Tool

The F-Tile Channel Placement Tool allows you to swiftly plan protocol placements and implementing F-Tile designs.

F-Tile Design Flow

Shows the flow for F-Tile including generating example designs, creating simulation models, and simulating the example designs.

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More Features

New IP

  • Split Analysis & Elaboration and Synthesis
  • Platform Designer AXI Timeout Bridge
  • AXI4-Lite support for the AXI Pipeline Bridge IP
  • GDR Multi-Rate IPs
  • Ethernet
  • CPRI
  • Direct PHY

Enhancements to Memory Support

  • RAM inferencing for clock enable usage to reduce power
  • Enhanced RAM Initialization Feature
  • Core Memory (LUTRAM, M20K) initialization
  • Randomize initialization value
  • Provide different seeds and random patterns
  • Target initialization per instance

Embedded Software

  • Wind River Linux Long Term Support, both source code and binary distributions, now available for Intel Agilex and Stratix 10 SoC FPGAs.

Partners

Questa*-Intel® FPGA Edition Software

The Questa*-Intel® FPGA Edition software from Mentor Graphics (A Siemens EDA company) is here! Questa*-Intel® FPGA Edition is the core simulation and debug engine of the Questa Verification Solution providing the latest in FPGA simulation technology. Questa-Intel FPGA Edition has up to 2.5x speedup for Verilog and 1.25x speedup for VHDL over the ModelSim*-Intel® FPGA Edition software. It is a full 64-bit version with support for both Windows 10 and Linux.

Documentation and Support

Find technical documentation, videos, and training courses for Intel® Quartus® Prime Design Software.

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Additional Resources

Learn more about how to purchase Intel® FPGA development tools and software.

Download

Get the complete suite of Intel® FPGA design tools.

Training

This page lists all the online and instructor-led courses currently available.

Buy

Find pricing information and purchase online.

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Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex​.

Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available ​updates. See backup for configuration details. No product or component can be absolutely secure.

Your costs and results may vary.