25G Ethernet Intel® FPGA IP

This IP core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium. The IP core includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The media access control (MAC) client side interface for the 25GbE IP core is a 64 bit Avalon® streaming interface (Avalon-ST). It maps to one 25.78125 Gbps transceiver. The IP core optionally includes Reed-Solomon forward error correction (FEC) for support of direct attach copper (DAC) cable.

Read the 25G Ethernet Intel® Arria® 10 FPGA IP user guide ›

Read the 25G Ethernet Intel® Stratix® 10 FPGA IP user guide ›

Read the 25G Ethernet Intel® Arria® 10 FPGA IP design example user guide ›

Read the 25G Ethernet Intel® Stratix® 10 FPGA IP design example user guide ›

25G Ethernet Intel® FPGA IP

 

Status

Production

Ordering Codes

25G Ethernet Intel® FPGA IP

IP-25GEUMACPHY (Arria® 10)

IP-25GEUMACPHY (Intel® Stratix® 10) – No FEC, No PTP support
IP-25GEUMACPHYF (Intel® Stratix® 10) – No FEC, With PTP support
IP-25GEUMACPHYFC (Intel® Stratix® 10) – With FEC, No PTP support
IP-25GEUMACPHYFFC (Intel® Stratix® 10) – With FEC, With PTP support