50G Ethernet Intel® FPGA IP

The 50G Ethernet Intel® FPGA IP core implements the 25G & 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet draft. The IP core includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The MAC client side interface for the 50 Gbps Ethernet IP core is a 128-bit Avalon® streaming interface (Avalon-ST). It maps to two 25.78125 Gbps transceivers.

Read the 50 Gbps ethernet IP core user guide ›

50G Ethernet Intel® FPGA IP

IP Quality Metrics

Basics

Year IP was first released

2017

First version of Intel Quartus Prime software supported

17.0

Ordering code

IP-50GEUMACPHY

Status

Early Access

Customer deliverables include the following:

Design file (encrypted source code or post-synthesis netlist)

Simulation model for ModelSim*- Intel FPGA Edition

Timing and/or layout constraints

Documentation with revision control

Readme file

Y

Any additional customer deliverables provided with IP

 

Parameterization GUI allowing end user to configure IP

Y

IP is enabled for Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog

Testbench language

 

Software drivers provided

N

Driver operating system (OS) support

 

Implementation

User interface

Avalon-ST (Datapath), Avalon-MM (Management)

IP-XACT metadata

N

Verification

Simulators supported

Mentor Graphics*, Synopsys*, Cadence*

Hardware validated

Intel Arria 10 GT, Intel Stratix 10 devices with H-Tile(s)

Industry standard compliance testing performed

N

If Yes, which test(s)?

 

If Yes, on which Intel FPGA device(s)?

 

If Yes, date performed

 

If No, is it planned?

Y

Interoperability

IP has undergone interoperability testing

Y

If yes, on which Intel FPGA device(s)

Intel Arria 10 GT device

Interoperability reports available

N