50G Ethernet Intel® FPGA IP
The 50G Ethernet Intel® FPGA IP core implements the 25G & 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet draft. The IP core includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The MAC client side interface for the 50 Gbps Ethernet IP core is a 128-bit Avalon® streaming interface (Avalon-ST). It maps to two 25.78125 Gbps transceivers.
50G Ethernet Intel® FPGA IP
The IP core provides standard media access control (MAC) and physical coding sublayer (PCS), and PMA functions shown in the following block diagram. The PHY comprises the PCS and PMA.
Features
PHY:
- Soft PCS logic that interfaces seamlessly to Intel® Agilex® F-Tile FPGA 51.5625 gigabits per second (Gbps) serial transceiver.
Frame structure control:
- Support for jumbo packets, defined as packets greater than 1,500 bytes.
- Receive (RX) cyclic redundancy check (CRC) removal and pass-through control. Transmit (TX) CRC generation.
- RX and TX preamble pass-through option for applications that require proprietary user management information transfer.
- TX automatic frame padding to meet the 64-byte minimum Ethernet frame length.
Frame monitoring and statistics:
- RX CRC checking and error reporting.
- Optional RX strict SFD checking per IEEE specification.
- RX malformed packet checking per IEEE specification.
- Optional fault signaling detects and reports local fault and generates remote fault, with IEEE 802.3ba-2012 Ethernet Standard Clause 66 support.
- Unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard.
Debug and testability:
- Programmable serial PMA local loopback (TX to RX) at the serial transceiver for self-diagnostic testing.
- Optional access to Intel® FPGA Debug Host Endpoint (ADME) for serial link debugging or monitoring PHY signal integrity.
User system interfaces:
- Avalon® Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers.
- Avalon® streaming (Avalon-ST) data path interface connects to client logic.
- Ready latency of 0 clock cycles for Avalon-ST TX interface.
- Hardware and software reset control.
IP Quality Metrics
Basics |
|
|---|---|
Year IP was first released |
2017 |
First version of Intel Quartus Prime software supported |
17.0 |
Ordering code |
IP-50GEUMACPHY |
Status |
Early Access |
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim*- Intel FPGA Edition Timing and/or layout constraints Documentation with revision control Readme file |
Y |
Any additional customer deliverables provided with IP |
|
Parameterization GUI allowing end user to configure IP |
Y |
IP is enabled for Intel FPGA IP Evaluation Mode Support |
Y |
Source language |
Verilog |
Testbench language |
|
Software drivers provided |
N |
Driver operating system (OS) support |
|
Implementation |
|
User interface |
Avalon-ST (Datapath), Avalon-MM (Management) |
IP-XACT metadata |
N |
Verification |
|
Simulators supported |
Mentor Graphics*, Synopsys*, Cadence* |
Hardware validated |
Intel Arria 10 GT, Intel Stratix 10 devices with H-Tile(s) |
Industry standard compliance testing performed |
N |
If Yes, which test(s)? |
|
If Yes, on which Intel FPGA device(s)? |
|
If Yes, date performed |
|
If No, is it planned? |
Y |
Interoperability |
|
IP has undergone interoperability testing |
Y |
If yes, on which Intel FPGA device(s) |
Intel Arria 10 GT device |
Interoperability reports available |
N |
Related Links
Documentation
- H-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Core Release Notes
- Dynamically generated hardware design examples within the Intel Quartus Prime software to easily test your custom configuration
- For Intel® Arria® 10 FPGAs: 50G ethernet design example user guide
- For Intel® Stratix® 10 FPGAs: Intel® Stratix® 10 H-Tile hard IP for ethernet design example user guide
Development Boards
Additional Resources
Find IP
Find the right Intel® FPGA Intellectual Property core for your needs.
Technical Support
For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.
IP Evaluation and Purchase
Evaluation mode and purchasing information for Intel® FPGA Intellectual Property cores.
Designing with Intel® FPGA IP
Learn more about designing with Intel® FPGA IP, a large selection of off-the-shelf cores optimized for Intel® FPGAs.
IP Base Suite
Free Intel FPGA IP Core licenses with an active license for Intel® Quartus® Prime Standard or Pro Edition Software.
I-Tested
Intel awards the interoperability-tested or I-Tested certification to verified Intel FPGA IP or Intel FPGA Design Solutions Network member IP cores.
Intel® FPGA Partner IP
Browse catalog of Intel® FPGA partner intellectual property cores in the Intel® Solutions Marketplace.
Design Examples
Download design examples and reference designs for Intel® FPGA devices.
IP Certifications
Intel is committed to providing Intellectual Property cores that work seamlessly with Intel® FPGA tools or interface specifications.
Contact Sales
Get in touch with sales for your Intel® FPGA product design and acceleration needs.