Intel® Agilex™ and Intel® Stratix® 10 FPGA E-Tile Hard IP

The Intel® Agilex™ and Intel® Stratix® 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible with the IEEE 802.3 High-Speed Ethernet Standard and the 25G and 50G Ethernet Specification, Draft 1.6 from the 25G Ethernet Consortium. The Intellectual Property (IP) core provides access to this hard IP at data rates of 10 Gbps, 25 Gbps, and 100 Gbps.

Read the E-tile Hard IP user guide ›

Read the E-tile Hard IP Intel® Stratix® 10 design examples user guide ›

E-tile Hard IP Intel® Stratix® 10 design example user guide ›

E-tile Hard IP Intel® Agilex™ design example user guide ›

Intel® Agilex™ and Intel® Stratix® 10 FPGA E-Tile Hard IP

Ethernet IP

Protocol

Number of Lanes and Line Rate

100GbE

100GBASE-KR4

100GBASE-CR4

CAUI-4

CAUI-2

4x25.78125 Gbps non-return-to-zero (NRZ) for copper backplane

4x25.78125 Gbps NRZ for direct-attach copper cable

4x25.78125 Gbps NRZ for low-loss links: Chip-to-chip or chip-to-module

2x53.1 Gbps PAM4 for low-loss links: Chip-to-chip, chip-to-module, and digital-to-analog converter (DAC)

25GbE

25GBASE-KR

25GBASE-CR

25GBASE-R AUI

25GBASE-R Consortium Link

Gbps for backplane

Gbps for direct-attach copper cable

Gbps for low-loss connections to external PHY modules

Gbps based on the 25G/50G consortium specification

10GbE

10GBASE-KR

10GBASE-CR

10.3125 Gbps for backplane

10.3125 Gbps Lanes for direct attach copper cable

 

Ordering Status

Production

Ordering Codes

Intel® Stratix® 10 FPGA H-Tile Hard IP for Ethernet Intel® FPGA IP Core

IP-ETH-ETILEHIP

IP-ETH-ETILEKRCR - To enable KR/CR (AN/LT) for E-Tile Ethernet Hard IP (10GE/25GE/100GE)