Intel® FPGA IP for PCIe*

PCI Express (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 gigatransfers per second (GT/s) to 32 GT/s and beyond. Intel® FPGA Intellectual Property (IP) for PCIe continues to scale as the PCI-SIG organization delivers next-generation specifications. Intel has been a member of PCI-SIG since 1992, and with each new generation of silicon, Intel continues to participate in PCI-SIG Compliance Workshops to ensure interoperability and conformance with current industry standards.

Intel® FPGA IP for PCIe*

The PCIe IP solutions include Intel’s technology-leading PCIe hardened protocol stack, which includes the transaction and data link layers, as well as a hardened physical layer. The later one includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). Intel's PCIe IP also includes optional soft IP blocks, such as Direct Memory Access (DMA) engines and Single-root I/O virtualization (SR-IOV). This unique combination of hardened and soft IP provides superior performance and flexibility for optimal integration.

Intel offers Intel FPGA® IP function-based PCIe IP solutions that have evolved with PCI-SIG’s protocol roadmap.

Intel also offers complementary soft IPs, which work with the tile-based hard IPs above for doing PCIe DMA and Switch functions.

Device Support and Number of Hardened PCIe IP Blocks

Device Family	Number of Hardened PCIe* IP Blocks	PCIe Link Speed 1.0 (2.5 GT/s)	PCIe Link Speed 2.0 (5.0 GT/s)	PCIe Link Speed 3.0 (8.0 GT/s)	PCIe Link Speed 4.0 (16.0 GT/s)	PCIe Link Speed 5.0 (32.0 GT/s)
Intel® Agilex™	1–3 per device	✓	✓	✓	✓	✓
Intel® Stratix® 10	1–4 per device	✓	✓	✓	✓
Intel® Arria®10	1–4 per device	✓	✓	✓
Intel® Cyclone® 10	1 per device	✓	✓
Intel® Cyclone® 10 GX	1 per device	✓	✓
Arria® V	1–2 per device	✓	✓
Cyclone® V GT	2 per device	✓	✓
Cyclone® V GX	1–2 per device	✓
Stratix® IV	2–4 per device	✓	✓
Cyclone® IV GX	1 per device	✓
Arria® II GZ	1 per device	✓	✓
Arria® II GX	1 per device	✓

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Device Configurations and Features Support

Interface Type		Avalon® streaming interface	Avalon® memory mapped	Avalon® memory mapped with DMA	SR-IOV	CvP / PRoP
Device/Configuration
Intel® Agilex™	Endpoint	Up to 5x16	Up to 5x16	Up to 5x16	Available	Up to 5 x16: CVP Init
Intel® Agilex™	Root Port	Up to 5x16	Up to 5x16	-	-	-
Intel® Stratix® 10	Endpoint	Up to 4x16	Up to 4x16	Up to 4x16	Available	Up to 4x16: CVP Init
Intel® Stratix® 10	Root Port	Up to 4x16	Up to 4x16	-	-	-
Intel® Arria® 10	Endpoint	Up to 3x8	Up to 3x4	1x8, 2x4, 2x8, 3x2, 3x4, 3x8	Available	Up to 3x8: CVP and PRoP
Intel® Arria® 10	Root Port	Up to 3x8	Up to 3x4	-	-	-
Intel® Cyclone® 10 GX	Endpoint	Up to 2x4	Up to 2x4	2x4	-	Up to 2x4: CVP and PRoP
Intel® Cyclone® 10 GX	Root Port	Up to 2x4	Up to 2x4	-	-	-
Stratix® V	Endpoint	Up to 3x8	Up to 3x4	1x8, 2x4, 2x8 3x2, 3x4, 3x8	Available	1: CVP Init and CVP Update 2: CVP Init and CVP Update
Stratix® V	Root Port	Up to 3x8	Up to 3x4	-	-	-
Arria® V GZ	Endpoint	Up to 3x8	Up to 3x4	1x8, 2x4, 2x8 3x2, 3x4, 3x8	-	1: CVP Init and CVP Update 2: CVP Init and CVP Update
Arria® V GZ	Root Port	Up to 3x8	Up to 3x4	-	-	-
Arria® V	Endpoint	Up to 1x8 and 2x4	Up to 1x8 and 2x4 (no x2)	1x8, 2x4	-	Up to 1x8 and 2x4 1: CVP Init and CVP Update 2: CVP Init
Arria® V	Root Port	Up to 1x8 and 2x4	Up to 1x8 and 2x4 (no x2)	-	-	-
Cyclone® V	Endpoint	Up to 2x4	Up to 2x4 (no x2)	2x4	-	Up to 2x4 1: CVP Init and CVP Update 2: CVP Init
Cyclone® V	Root Port	Up to 2x4	Up to 2x4 (no x2)	-	-	-

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Intel® FPGA IP for PCIe*