Serial Lite IV Intel® FPGA IP Core
The Serial Lite IV Intel FPGA Intellectual Property (IP) core is suitable for high-bandwidth data communication for chip-to-chip, board-to-board, and backplane applications.
Serial Lite IV Intel® FPGA IP Core
Serial Lite IV IP core incorporates a media access control (MAC), physical coding sublayer (PCS), and physical media attachment (PMA) block. The IP supports data transfer up to 56 Gbps per lane with a maximum of eight PAM4 lanes in a single link or 28 Gbps per lane with a maximum of 16 non-return-to-zero (NRZ) lanes. This protocol offers high bandwidth, low overhead frames, low I/O count, and supports high scalability in both numbers of lanes and speed. The IP is easily reconfigurable with support of a wide range of data rates with Ethernet PCS mode of the E-Tile transceiver and the F-Tile transceiver.
This IP supports two transmission modes:
- Basic mode—This is a pure streaming mode where data is sent without the start-of-packet, empty cycle, and end-of-packet to increase bandwidth. The IP takes the first valid data as the start of a burst.
- Full mode—This is the packet mode of data transfer. A burst and sync cycle is sent at the start and at the end of a packet as delimiters.
Features
Feature | Description |
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Data Transfer |
|
PCS |
|
Error Detection and Handling |
|
Interfaces |
|
IP Quality Metrics
Basics |
|
---|---|
Year IP was first released |
2019 |
Latest version of the Intel® Quartus® Prime software supported |
19.4 |
Status |
Advanced |
Deliverables |
|
Customer deliverables include the following:
|
Y for all |
Any additional customer deliverables provided with IP |
Testbench and design examples |
Parameterization GUI allowing end user to configure IP |
Y |
IP is enabled for Intel FPGA IP Evaluation Mode Support |
Y |
Source language |
Verilog |
Testbench language |
Verilog |
Software drivers provided |
N |
Driver OS Support |
N |
Implementation |
|
User interface |
Avalon® Streaming |
IP-XACT metadata |
N |
Verification |
|
Simulators supported |
NCSim, ModelSim, VCS/VCSMX |
Hardware validated |
Intel® Agilex™ FPGA Development Kit, Intel Stratix 10 FPGA Signal Integrity Development Kit |
Industry-standard compliance testing performed |
N |
If Yes, which test(s)? |
N/A |
If Yes, on which Intel FPGA device(s)? |
N/A |
If Yes, date performed |
N/A |
If No, is it planned? |
N |
Interoperability |
|
IP has undergone interoperability testing |
N/A |
If yes, on which Intel FPGA device(s) |
N/A |
Interoperability reports available |
N/A |
Related Links
Documentation
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