Stratix® V FPGAs: Delivering the Highest System Integration

Table 1. Hard IP Functions Built with the Embedded HardCopy Block

Protocols

Applications

PCIe Gen3, Gen2, Gen1

PHY/MAC, data link, transaction layers

40G/100G

MLD/PCS – gearbox, block sync,
alignment marker, reorder virtual channel,
async buffer/deskew, block striper/destriper,
scrambler/descrambler

Table 2. Integrated Hard IP Blocks in Transceivers and Core

Protocols

Applications

Hard IP Per Transceiver Channel (PCS)

Interlaken

Gearbox, block sync, 64B/67B, frame sync,
scrambler/descrambler, CRC-32,
async buffer/deskew

10 Gigabit Ethernet (GbE) (10GBASE-R)

Gearbox, block sync, scrambler/descrambler,
64B/66B, rate matcher

PCIe Gen3, Gen2, Gen1

Word aligner, lane sync state machine, deskew,
rate matcher, 8B/10B, gearbox, 128B/130B, PIPE-8/16/32

Serial RapidIO® 2.0

Word aligner, lane sync state machine, deskew, rate matcher, 8B/10B

CPRI/OBSAI

Word aligner, bit slip (determinist latency), 8B/10B

Core Hard IP

DSP

Up to 3,510 new high-performance, variable-precision DSP blocks in the core

Embedded Memory

Up to 2,560 M20K embedded memory blocks

Table 3. Interlaken Savings Implementation

Hardened IP for Protocol

Logic Element Savings

24 Channels of Interlaken

120K

2 PCIe Gen3 x8 Cores

250K

Total LE Savings

370K