Hardware acceleration, particularly in the form of custom logic, is helping wireless networks, cloud service providers, and other enterprises meet rapidly increasing needs for performance, lower power, and lower total cost of ownership. In high-bandwidth wireless services, for example, 5G demands higher clock rates within a limited power budget.
In early stages, programmable products for wireless equipment offer design advantages over fixed hardware for accelerating certain functions, especially as networks continue to evolve. In cloud data centers, custom logic can accelerate algorithms related to storage, security, and other functions. Edge and embedded applications may benefit from acceleration for AI inferencing. Acceleration can also support the transition to the latest 8K high definition video standards in challenging thermal budgets.
When it comes to hardware design, system architects have several types of custom logic solutions to choose from. FPGAs, structured ASICs, and ASICs are all part of the custom logic continuum. To balance flexibility, performance, power, and total cost of ownership needs, as well as time to market requirements, architects will need to choose the hardware type best suited to their circumstances.
Field programmable gate arrays (FPGAs) are integrated circuits with a programmable hardware fabric. The circuitry inside an FPGA is designed to implement a wide variety of different functions and can be reprogrammed to perform these functions as needed. As a result, FPGAs are typically an excellent choice in terms of flexibility and fast time to market.
FPGAs are prefabricated and programmed by the customer in their labs or in the field. They do not require non-recurring engineering cost (NRE) and can help innovators get to market extremely fast. This makes FPGAs a great option for differentiation in a quickly changing environment.
As new features mature, it can be more economical and power efficient to harden integrated circuit designs. Application specific integrated circuits (ASICs) are purpose-built and mass produced for a specific function. Unlike FPGAs, they cannot be reprogrammed, and they require a significant NRE investment.
With a standard cell-based ASIC, every layer of the integrated circuit must be customized. This requires specialized design teams and software tools designing for intended functionality, as well as making significant investments in design for test (DFT) architecture development to make sure the design is manufacturable and has good quality.
A structured ASIC is an incremental step between an FPGA and a cell-based ASIC. Structured ASICs start with a common base array with logic, memory, I/O, transceivers, and a hard processor system. Designers need only to customize interconnect, skipping many of the steps involved in cell-based ASIC design flow, and focusing instead on implementing the desired custom functionality. In essence, a structured ASIC offers lower power consumption with a lower unit cost compared to FPGAs, and a faster time to market with a lower NRE compared to cell-based ASICs.
What to Choose and When?
Designers and system architects must balance flexibility, performance, power consumption, and total cost of ownership with time to market requirements to make a custom logic technology solution selection.
Performance and Power Consumption
To maximize performance per watt, cell-based ASICs may be the best choice at the expense of higher up-front NRE investment and longer design cycles compared to FPGAs or structured ASIC devices. This choice also assumes the product does not need reprogrammability or changes to algorithms during the product lifecycle.
Development and Production Costs
For projects concerned with development costs, either structured ASICs or FPGAs are likely to be the best choices. Although an ASIC has the lowest manufacturing cost per unit, it has the highest NRE cost, so this option may only make sense for designs with significantly higher production volume expectations. FPGA designs generally do not require up-front NRE costs and can scale from hundreds to hundreds of thousands of units. Thanks to its simplified design flow and customization, a structured ASIC has a lower development cost compared to cell-based ASICs on similar process nodes and can be an economical approach to save cost and power on lower volume.
Time to Market
Projects concerned with time to market above all other factors should consider FPGAs first. Depending on the complexity of the design, an FPGA can take weeks or months to design. A structured ASIC takes about six to nine months depending on complexity, with a cell-based ASIC requiring somewhere between 18 to 24 months.
Planning a Migration Path
When implementing custom logic solutions, it’s important to consider the possible migration path from one type of custom logic technology to another to support life cycle needs from prototyping and early production to mass production. A design initiated on an FPGA could be hardened on either a structured or cell-based ASIC. Likewise, system architects can migrate from a structured ASIC to cell based in order to massively scale up volume.
However, migrating from one type of hardware to another could potentially require changes not only to the printed circuit board (PCB) but also to intellectual property, as well as processors and associated software development. These changes add time and cost to transition.
Intel® FPGAs, Structured ASICs, and Cell-Based ASICs
Using multiple vendors for FPGA, structured ASIC, and cell-based ASIC development can lead to challenges with compatibility and translating the design from one development process to another, slowing time to market.
In offering a complete continuum of custom logic solutions, Intel streamlines migration and reduces the amount of potential rework. Now designers have a choice of solutions to optimize flexibility, power, performance, cost, and time to market requirements for each project and throughout the product life cycle. Intel® FPGAs offer a fast time to market with the highest flexibility. Intel® eASIC™ structured ASICs reduce power consumption and per-device costs while offering a lower NRE and faster time to market than cell-based ASICs.
This enhanced selection is also supported with compatible hard processors and security systems leveraged from Intel® FPGAs and custom package solutions. These make it possible for manufacturers to avoid costly PCB redesign efforts.
Intel® FPGA products span a range of families, including the well-received Intel® Agilex™ and Intel® Stratix® series. Built for high speed in a small power envelope, Intel® FPGAs help system architects stay within their performance, power, and price limitations while achieving a fast time to market. And because they share common IP with the latest structured ASICs from Intel, these FPGAs offer advantages as a starting point for designs that may migrate to a structured ASIC in the future.
Intel® eASIC™ Devices
Intel® eASIC™ devices are structured ASICs designed to help lower power and per unit costs relative to FPGAs with lower NRE and faster time to market compared with cell-based ASICs.
The Intel® eASIC™ N5X for the first time adds a quad-core hard processor system and secure device manager, adapted from Intel® Agilex™ FPGAs.
Interfaces including JESD204 ADC/DAC and connectivity protocols including 10/25G Ethernet are available for both Intel® FPGA and Intel® eASIC™ N5X Devices to ease design migration.
Intel® easicopy™ Devices
For a seamless path from structured to cell-based ASICs, Intel® easicopy™ devices enable the transition to very high volume production. These devices work by implementing the customer’s design in standard cell gates but borrowing some of the processor, security, transceiver, and IO IP from the structured ASIC families.
In addition to hardware, Intel offers developer tools and software. Developer tools such as Intel® Quartus® Prime Pro Edition Software help reduce the development time and cost of FPGA designs.
Intel® eASIC™ eTools offer a framework for design conversion and validation using a combination of internally developed and industry standard third-party tools. This includes synthesis and simulation libraries, IP wrappers to implement eASIC functions, as well as scripts for code validation and running third-party synthesis and simulation tools. Intel® Quartus® software Platform Designer is used for the hard processor system configuration. DSP Builder for Intel® FPGAs can also output FPGA and eASIC™-ready RTL code.
With a diverse portfolio of silicon, Intel enables system architects to design incredibly customized solutions. Only Intel provides Intel® Xeon® processors, Intel® FPGAs, ASICs, and new structured ASIC devices. This assortment comprises a custom logic continuum that enables architects to meet their unique needs for time to market, performance, power, and cost.