Product Collection
MAX® II CPLD
Status
Launched
Launch Date
Q1'14
Lithography
180 nm

Resources

Equivalent Macrocells
1700
Pin-to-pin Delay
7 ns
User Flash Memory
8 Kb

Features

Boundary-scan JTAG
Yes
JTAG ISP
Yes
Fast Input Registers
Yes
Programmable Register Power-up
Yes
JTAG Translator
Yes
Real-time ISP
Yes
MultiVolt I/Os†
1.5, 1.8, 2.5, 3.3, 5.0
I/O Power Banks
4
Maximum Output Enables
272
LVTTL/LVCMOS
Yes
32 bit, 66 MHz PCI Compliant
Yes
Schmitt Triggers
Yes
Programmable Slew Rate
Yes
Programmable Pull-up Resistors
Yes
Programmable GND Pins
Yes
Open-drain Outputs
Yes
Bus Hold
Yes

Package Specifications

Package Options
F256, F324
Package Size
17 mm x 17mm, 19mm x 19mm

Supplemental Information

Additional Information