Siemens EDA* AXI Verification IP Suite
The Siemens EDA AXI Verification IP Suite (Intel® FPGA Edition) provides bus functional models (BFMs) to simulate the behavior and to facilitate the verification of intellectual property (IP) that conforms to the Advanced Microcontroller Bus Architecture Advanced eXtensible Interface (AMBA* AXI) Protocol, with restrictions to simplify the application programming interface (API) for you.
Read the Mentor Verification IP Altera Edition AMBA AXI3/AXI4 User Guide ›
Read the Mentor Verification IP Altera Edition AMBA AXI3/4 User Guide ›
Read the Mentor Verification IP Altera Edition AMBA AXI4-Lite User Guide ›
Read the Mentor Verification IP Altera Edition AMBA AXI4-Stream User Guide ›