TMC-20210: Paths Failing Setup Analysis with High Routing Delay Added for Hold

Description

Violations of this rule identify paths that fail setup analysis with high routing delay added for hold. During routing, the Fitter may add wire between register paths to increase delay to meet hold time requirements. Excessive additional wire can indicate an error with the constraint. The cause of such errors is typically incorrect multicycle transfers between multi-rate clocks, and between different clock networks.

Parameters

Name Description Type Default Value Min Value Max Value
maximum_setup_slack Reports a violation for timing paths that have a setup slack below the value of this parameter. double 0.0    
to_clock_filter Reports a violation for timing paths that end at a register in a clock domain that matches the value of this parameter. string *    
minimum_number_of_adders Reports a violation for timing endpoints that are preceded by a number of independent adder chains greater than or equal to this value. integer 3    
minimum_number_of_soft_mult_chains Reports a violation for timing endpoints that are preceded by a number of independent adder chains that are implementing multiplier logic greater than or equal to this value. integer 2    

Recommendation

Review the timing paths to determine whether the Fitter adds excessive wire to meet hold timing. Verify that timing constraints, especially multicycles, are set properly. Refer to Wires Added for Hold in Intel Quartus Prime Pro Edition User Guide: Design Optimization for more information.

Severity

Medium

Tags

Tag Description
route Design rule checks which pertain to the Compiler's Route stage.

Device Family

  • Intel®Stratix® 10
  • Intel®Agilex™
  • Intel®Arria® 10
  • Intel®Cyclone® 10 GX