TMC-20216: Paths Failing Setup Analysis with Inferred-RAM Shift Register Endpoints

Description

Violations of this rule identify setup-failing paths that begin or end with shift registers implemented with inferred RAM blocks.

Implementing shift registers this way can save area, but can also be detrimental to timing.

Parameters

Name Description Type Default Value Min Value Max Value
maximum_setup_slack Reports a violation for timing paths that have a setup slack below the value of this parameter. double 0.0    
to_clock_filter Reports a violation for timing paths that end at a register in a clock domain that matches the value of this parameter. string *    
minimum_number_of_adders Reports a violation for timing endpoints that are preceded by a number of independent adder chains greater than or equal to this value. integer 3    
minimum_number_of_soft_mult_chains Reports a violation for timing endpoints that are preceded by a number of independent adder chains that are implementing multiplier logic greater than or equal to this value. integer 2    

Recommendation

In the Analysis & Synthesis settings, set "Auto Shift Register Replacement" to Off. Use an AUTO_SHIFT_REGISTER_RECOGNITION OFF assignment to disable shift register replacement for the replaced registers.

Severity

Medium

Tags

Tag Description
ram Design rule checks related to M20k blocks inside the FPGA fabric.

Device Family

  • Intel®Stratix® 10
  • Intel®Agilex™
  • Intel®Arria® 10
  • Intel®Cyclone® 10 GX