What’s New in 21.1
Intel® Quartus® Prime Pro Edition Software v21.1 supports the newest FPGA family:
Intel® Agilex™ FPGAs
The Intel® Agilex™ FPGA family leverages heterogeneous 3D system-in-package (SiP) technology to integrate Intel’s first FPGA fabric built on 10 nm process technology and 2nd generation Intel® Hyperflex™ FPGA Architecture to deliver up to 40% higher performance1 or up to 40% lower power1 for applications in Data Center, Networking, and Edge compute. Intel® Agilex™ SoC FPGAs also integrate the quad-core Arm Cortex-A53 processor to provide high system integration.
The Intel® Quartus® Prime Pro Edition Software v21.1 is an intuitive design environment that will help you meet your power and performance requirements and reduce your overall development effort. Features in the v21.1 release include:
- Improvements for Intel Agilex FPGA power, performance, runtime, memory, and logic utilization
- New and improved Design Assistant design rules for synthesis, clock domain crossing (CDC), reset domain crossing (RDC), and timing
- Hierarchical grouping of design rule checking (DRC)
- Rule-tagging and filtering
- DRC waiver mechanism
- New ease-of-use reports for static timing analysis, design closure, synthesis, and undefined entities
- More cross-probing and runtime improvements for reports
- Locate SDC constraints in a file
- Faster ECO compiles for post-fit tap targets in Signal Tap II Logic Analyzer
- Flow-Resume feature
- Improved GUI display for higher resolution monitors
- Remote debug over Ethernet and PCIe using Nios® II processor
- Mark signals for debug (Beta) feature for register transfer level (RTL) development
A powerful feature that allows you to preserve large block placement from a compilation and do additional compilation sweeps with this placement fixed.
Documentation and Support
Find technical documentation, videos, and training courses for Intel® Quartus® Prime Design Software.
Product and Performance Information
This comparison is based on the Intel® Agilex™ FPGA and SoC family vs. Intel® Stratix® 10 FPGA using simulation results and is subject to change. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest forecast, schedule, specifications, and roadmaps.