Article ID: 000074415 Content Type: Troubleshooting Last Reviewed: 12/01/2017

Is the Clock Phase Alignment (CPA) block of the Altera LVDS IP supported for all SERDES factors in Stratix 10 devices?

Environment

  • Intel® Quartus® Prime Pro Edition
  • LVDS SERDES Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Clock Phase Alignment (CPA) block of the Altera® LVDS IP in Intel® Stratix® 10 devices is supported for all SERDES factors from Quartus® Prime Pro version 17.1 onwards under the following conditions:

    • The Use external PLL option is turned off.
    • The IP core functional mode is TX, RX Non-DPA, or RX DPA-FIFO.
    • The tx_outclock phase shift is a multiple of 180°

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs