Article ID: 000074443 Content Type: Troubleshooting Last Reviewed: 11/22/2023

What is the maximum FIFO depth for command fifo, response fifo, and urgent fifo in Mailbox Client Intel® Stratix® 10 FPGA IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Altera S10 Mailbox Client Core
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Before Intel® Quartus® Prime Pro Edition Software release version v19.1, the range was 1-2048.


    Starting from Intel® Quartus® Prime Pro Edition Software release version v19.1, the range is 1-1024.

     

    Resolution

    Users will need to adjust the FIFO depth manually from 1-1024 when migrating the design to Intel® Quartus® Prime Pro Edition Software release version v19.1.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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