Article ID: 000074445 Content Type: Error Messages Last Reviewed: 02/11/2023

Error (15065): Clock input port inclk[0] of PLL <PLL instance name> must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block

Environment

  • Intel® Quartus® Prime Lite Edition
  • Intel® Quartus® Prime Standard Edition
  • Internal Oscillator Intel® FPGA IP
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    Description

    This error may be seen in Intel® Quartus® Prime Standard Edition Software when the reference clock input of a phase-locked loop (PLL) is connected to the output of the Internal Oscillator IP in Intel MAX® 10 devices.

    Resolution

    To avoid this error, you should not feed the reference clock input of a phase-locked loop (PLL) with the output of the Internal Oscillator IP .

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs