Article ID: 000074467 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I see Verilog files when I generate VHDL files for the DDR/DDR2 High Performance (HP) Controller?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The HDL is always generated as Verilog for the purposes of synthesis. For doing simulation we generate a simgen model of <variation_name>_phy.vho for VHDL users.

Starting from Quartus II software version 7.2, the simulation tab in the IP Megawizard does not give an option for the language when generating simulation model, the simulation model is generated in the same language as the top level file.

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Stratix® II FPGAs