Description
The HDL is always generated as Verilog for the purposes of synthesis. For doing simulation we generate a simgen model of <variation_name>_phy.vho for VHDL users.
Starting from Quartus II software version 7.2, the simulation tab in the IP Megawizard does not give an option for the language when generating simulation model, the simulation model is generated in the same language as the top level file.