Article ID: 000074553 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why is tREFI value in simulation and board measurement different from what is set in Altmemphy and UniPHY based DDR2 SDRAM memory controller?

Environment

  • Quartus® II Subscription Edition
  • LPDDR2 SDRAM Controller with UniPHY Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    tREFI result in simulation and on the board might be larger than expected if you set tREFI to less than 7.8us in DDR/DDR2/LPDDR2 MegaWizard.

    DDR/DDR2/LPDDR2 SDRAM IP has MEM_TREFI parameter which defines tREFI parameter in terms of memory clock cycles.

    Since the minimum value of this parameter is limited to 780, tREFI becomes larger when memory clock is slower.

    For example, tREFI for DDR2 SDRAM should be 3.9us at >85C. But if DDR2 memory clock is 125MHz(8ns), minimum tREFI value can be 8ns x 780 = 6.24us.

    tREFI for DDR should be 7.8us. But if DDR memory clock is 76.9MHz (13ns), minimum tREFI value can be 13ns x 780 = 10.14us.

    Resolution

    As a workaround, if DDR memory clock is below 100MHz or if you set tREFI to <7.8us on DDR2 memory, you can change MEM_TREFI parameter in

    *ddrx_controller_wrapper (Altmemphy based IP) file or *_c0 (UniPHY based IP) file to correct tREFI value.

    This issue is planned to be fixed in a future version of Quartus® II software.

    Related Products

    This article applies to 14 products

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