Despite LVDS SERDES Intel® FPGA IP User Guide stating in section LVDS SERDES IP Core PLL Settings ,Table 10. PLL Settings Tab:
" This option allows you to access all of the available clocks from the PLL and use advanced PLL features such as clock switchover, bandwidth presets, dynamic phase stepping, and dynamic reconfiguration."
However, due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.4, you may see the following error message:
Error(18694): The reference clock on PLL "external_pll|external_pll|altera_iopll_i|c10gx_pll|iopll_inst", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.
This issue is fixed in Intel® Quartus® Prime Pro Edition software version 20.1.