Article ID: 000075320 Content Type: Troubleshooting Last Reviewed: 08/22/2012

DDR2 and DDR3 Designs Using Hard Memory Controller May Not Close Timing on Arria V and Cyclone V Devices

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    This problem affects DDR2 and DDR3 products.

    DDR2 and DDR3 designs using the hard memory controller on Arria V or Cyclone V devices may not close timing.

    Resolution

    The following are possible workarounds for this issue:

    Workaround One:

    Add the following false paths to the UniPHY SDC file (submodules/<core_name>_p0.sdc):

    set_false_path -from *|*c0|hmc_inst~FF_* -to *p0|*umemphy|*lfifo~LFIFO_IN_READ_EN_DFF set_false_path -from *|*p0|*umemphy|hphy_inst~FF_* -to *p0|*umemphy|*vfifo~INC_WR_PTR_DFF set_false_path -from *|*c0|hmc_inst~FF_* -to *p0|*umemphy|*vfifo~QVLD_IN_DFF set_false_path -from *|*p0|*umemphy|hphy_inst~FF_* -to *p0|*umemphy|*altdq_dqs2_inst|phase_align_os~DFF*

    The above paths are hard transfers which will function correctly. Cutting these paths sidesteps incorrect delay models.

    Workaround Two:

    To decrease the sequencer clock domain frequency (clock_pll_avl_clk), open submodules/<core_name>_p0_parameters.tcl in a text editor and increase by one the most-significant digit of ::GLOBAL_dut_if0_p0_pll_div(5).

    For example, change the following:

    set ::GLOBAL_dut_if0_p0_pll_mult(5) 5333333� set ::GLOBAL_dut_if0_p0_pll_div(5) 6000000�

    to the following:

    set ::GLOBAL_dut_if0_p0_pll_mult(5) 5333333� set ::GLOBAL_dut_if0_p0_pll_div(5) 7000000�

    Open submodules/<core_name>_pll0.sv in a text editor and change the value of PLL_NIOS_CLK_FREQ_STR to match the preceding step.

    For example, change the following:

    parameter PLL_NIOS_CLK_FREQ_STR = "88.888883 MHz";�

    to the following:

    parameter PLL_NIOS_CLK_FREQ_STR = "76.190476 MHz";�

    This issue will be fixed in a future version.

    Related Products

    This article applies to 2 products

    Cyclone® IV FPGAs
    Arria® V FPGAs and SoC FPGAs