Article ID: 000075369 Content Type: Troubleshooting Last Reviewed: 07/20/2018

Why do I see unconstrained clocks ru_clk and flash_se_neg_reg in the Dual Boot IP timing report?

Environment

  • Dual Configuration Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You might see timing violations in the timing report when you use the dual boot intellectual property (IP) of Intel® MAX® 10 FPGAs as follow: 

    TimeQuest Timing Analyzer/Unconstrained Path/Clock Status Summary: ru_clk and flash_se_neg_reg

    Resolution

    The Timing Analyzer in the Intel® Quartus® Prime software identifies these ports as clocks, because they are unconstrained in the SDC file. The dual boot IP is not shipped with an SDC file.

    You are required to add the following constraints.

    #constraint for avalon clock of dual boot IP

    create_clock -name inclk -period 12.5 [get_ports {inclk}]

    #set ru_clk =1/2 of avalon clock

    create_generated_clock -name ru_clk -source [get_ports {inclk}] -divide_by 2 [get_keepers {i2c_rsu:u0|altera_dual_boot:dual_boot_0|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|ru_clk}]

    #set flash_se_neg_reg =1/2 of avalon clock

    create_generated_clock -name flash_se_neg_reg -source [get_ports {inclk}] -divide_by 2 [get_keepers {i2c_rsu:u0|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg}]

    The Dual Boot IP core user guide is scheduled to be updated in a future release.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs