Article ID: 000075482 Content Type: Troubleshooting Last Reviewed: 04/03/2023

Why does my PCIe link get stucked in the Detect state for Arria® II and Stratix® IV devices?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the PCIe Hard IP PMA, the link may get stucked in the Detect.Active state.

    This is because the transceiver receiver detect logic not returning a PHYSTATUS pulse on the PIPE interface to the Hard IP core if the low period of two consecutive TxDetectRx is less than 544 ns. 

    This problem affects Stratix® IV GX, Stratix® IV GT, and Arria® II GX devices.

    Resolution

    Manually change the Hard IP reset logic to assert the crst and srst signal for at least 1 us. 

    You can use the following files to view the changes required for both Avalon® streaming and Avalon® memory mapped interfaces to satisfy the requirement above.

    • top_rs_hip (.v): Added reset logic can be found on lines 181-211.  Put these lines in your <instantiation name>_rs_hip.v file for Avalon streaming interfaces.
    • pcie_compiler_0 (.v) : Added reset logic can be found on lines 648-684.  Put these lines in your instantiation file for Avalon memory mapped interfaces.
    • pcie_compiler_0 (.vhd): Added reset logic can be found on lines 775-810.  Put these lines in your instantiation file for Avalon memory mapped interfaces.

    Related Products

    This article applies to 4 products

    Stratix® IV GT FPGA
    Stratix® IV GX FPGA
    Cyclone® IV GX FPGA
    Arria® II GX FPGA