Article ID: 000076539 Content Type: Product Information & Documentation Last Reviewed: 01/09/2014

How can I observe the PIPE interface signals of Stratix IV, Cyclone V and Arria V GX PCIe HIP using Signaltap II?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

If you want to use Signaltap™ II to observe the PIPE interface signals of the Stratix® IV, Cyclone® V and Arria® V GX Hard IP for PCI Express®, please set test_in[11:8] of the PCIe® core to 4'b0011. And then you can observe the PIPE interface signals on test_out port. Please notice that you should use tx_clkout[0] (pld8gtxclkout) of the GXB module instead of core_clk_out as the capture clock signal.

The following bits are defined for test_out:
[7:0]—txdata
[8]—txdatak
[9]—txdetectrx
[10]—txelecidle
[11]—txcompl
[12]—rxpolarity
[14:13]—powerdown
[22:15]—rxdata
[23]—rxdatak
[24]—rxvalid
[63:25]—Reserved.

Related Products

This article applies to 10 products

Stratix® IV GX FPGA
Stratix® IV GT FPGA
Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Arria® V GX FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V GT FPGA
Arria® V ST SoC FPGA