Article ID: 000076558 Content Type: Troubleshooting Last Reviewed: 06/15/2015

The Quartus II software no longer allows MAX 10 device designs to use non-existent connectivity between DPCLK pins and the clock network

Environment

  • Quartus® II Subscription Edition
  • Clock
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The Quartus II software release versions 14.1 and 15.0 can erroneously allow MAX 10 device designs to use non-existent connectivity between DPCLK pins and the clock network; specifically, the software could allow connectivity from DPCLK0 to GCLK[4] and from DPCLK2 to GCLK[9]. If you use either of these non-existent paths in your design, the software does not indicate any issues, but produces a non-functional design on the FPGA. Refer to the MAX 10 Clocking and PLL User Guide for allowable DPCLK to GCLK connectivity: https://documentation.altera.com/#/00003866-AA.

    Resolution

    There is no workaround. This issue will be fixed in an upcoming software release.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs