Article ID: 000077039 Content Type: Error Messages Last Reviewed: 09/11/2012

Warning: Can't achieve requested value xx degrees for clock output of parameter phase shift -- achieved value of xx degrees.

Environment

  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You specified a phase shift value for the PLL output clock. However, the Quartus® II software could not achieve your specified phase shift value. Instead, the Quartus II software selected a nearest available phase shift value. If the phase shift value selected by the Quartus II software is acceptable, nothing further needs to be done.

    The available phase shift step depends on the PLL's VCO period divide by 8. The example below provides a detailed explanation.

    fin, PLL inclk: 100MHz
    fout, PLL output clock: 300MHz (period: 3.333ns)
    VCO frequency: 600MHz (period: 1.667ns)
    M counter: 6

    Phase shift per step = 1.667ns / 8 = 208.375ps
    On the 300MHz PLL output clock with 3.333ns period, 208.375ps equivalent to 22.5 degree per step.

    In conclusion, the phase shift resolution for the PLL can be changed by adjusting the VCO frequency.

    Related Products

    This article applies to 1 products

    Stratix® III FPGAs