Article ID: 000077340 Content Type: Troubleshooting Last Reviewed: 03/27/2018

Why HPS hangs when HPS to FPGA bridge is connected to AXI Bridge IP together with other bus master(s)?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® FPGA Interconnect
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    HPS may hang while accessing to AXI Bridge which is interfaced to more than one bus master.

    AXI Bridge slave interface will constantly back pressure master access when one of the master issue read/write transaction to it.

    Resolution

    As temporary workaround, add an Avalon MM Pipeline Bridge in between the bus masters and the AXI Bridge to resolve AXI Bridge multiple master signals handling issue. Actual AXI Bridge IP fixed is schedule in future Quartus release.

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 SX SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V SX SoC FPGA

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