Article ID: 000077357 Content Type: Troubleshooting Last Reviewed: 02/16/2023

Why does the Arria 10 ATX PLL pll_cal_busy signal assert even without ATX PLL calibration?

Environment

  • Intel® Quartus® Prime Pro Edition
  • PLL Reconfig Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see the pll_cal_busy signal of the Intel® Arria® 10 ATX PLL assert when the internal configuration bus is returned to the PreSICE even though no ATX PLL calibration is requested. This is a known issue with the Intel® Arria® 10 PreSICE.

     

     

    Resolution

    If ATX PLL calibration is not required, write the value of 2'b00 to offset address 0x100[1:0] before the internal configuration bus is returned to the PreSICE.

    This has already been fixed in Intel® Quartus® Prime Pro Edition Software 17.0. 

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs