Why is my JTAG chain broken when the HPS_nRST or HPS_nPOR signal is asserted?

The hard processor system (HPS) JTAG port (HPS_TCK, HPS_TMS, HPS_TDI, HPS_TDO) of Arria® V SoC and Cyclone® V SoC devices is held in Test Logic Reset when either HPS_nRST or HPS_nPOR is asserted.

To perform FPGA configuration or boundary scan ensure one of the following is true:

• The HPS port is not included in the JTAG chain while HPS_nRST or HPS_nPOR is asserted.
• The HPS_nRST or HPS_nPOR is deasserted before using the JTAG chain.

Note that the HPS JTAG port is not used for configuration or boundary-scan and is only used for debugger access.