Article ID: 000077948 Content Type: Troubleshooting Last Reviewed: 11/19/2013

Can I use Report DDR for ALTDQ_DQS2 megafunction?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

In the Quartus® II software, the Report DDR panel does not support ALTDQ_DQS2 megafunction. The Report DDR panel is a static timing analysis macro specific to Altera® memory interface IP. It calls the <core name>_report_timing.tcl script in the back-end.

The ALTDQ_DQS2 and ALTDDIO megafunctions do not have this macro and don't come with a script. Users are expected to write their own timing constraints in the form of synopsys design constraint (.sdc) files. Timing analysis is performed the same as for any other design.

Related Products

This article applies to 3 products

Stratix® V GS FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA