Article ID: 000078261 Content Type: Troubleshooting Last Reviewed: 12/12/2013

Why does my LVDS interface fail hold timing in Cyclone V 300GT devices in the Fast 0C timing corner?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 12.0 SP2 and earlier, you may see these timing violations in your Cyclone® V 300GT design. There is an problem with the Fast 0C timing model for these devices.

    Resolution

    This problem has been fixed beginning with the Quartus II software version 12.1.

    Related Products

    This article applies to 1 products

    Cyclone® V GT FPGA