Article ID: 000078481 Content Type: Troubleshooting Last Reviewed: 08/03/2023

Why can't the fractional PLL (fPLL) parameters be changed using the Resource Property Editor or Chip Planner when targeting Stratix® V, Arria® V, or Cyclone® V devices?

Environment

  • Quartus® II Software
  • Arria® V Transceiver PLL Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    It is not possible to edit the parameters of fPLLs using the Resource Property Editor or Chip Planner in the Quartus® II software when designing with Stratix® V, Arria® V, or Cyclone® V devices.

    Resolution

    Utilize the PLL Reconfiguration feature to dynamically update the fPLL parameters.

    For further details, refer to AN661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig Megafunctions (PDF)

    Related Products

    This article applies to 11 products

    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Cyclone® V GX FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA
    Cyclone® V E FPGA
    Cyclone® V SE SoC FPGA