Article ID: 000079038 Content Type: Troubleshooting Last Reviewed: 11/17/2011

Unable to Configure DSP Resource Optimization Check Box in FFT Parameter Editor for Stratix V Devices

Environment

  • Quartus® II Subscription Edition
  • Transforms
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    In QDR II and QDR II SRAM Controllers with UniPHY targeting Arria V or Cyclone V devices, with read latency not equal to 2, the complimentary clock mem_cq_n is not used for capture, therefore the pin is unused.

    In cases where read latency equals 2, mem_cq_n serves as the capture clock and mem_cq is unused.

    This issue affects QDR II and QDR II SRAM Controllers targeting Arria V and Cyclone V devices, where read latency does not equal 2.

    Resolution

    You can manually enable this option by modifying the generated variation file manually, from DSP ARCH g => 0, to DSP ARCH g => 1.

    Solution Status

    This issue will be fixed in a future release of the FFT MegaCore function.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs