Description
When generating a configuration file using the Quartus II software version 2.2 SP1 and earlier, a negative phase delay may be incorrectly implemented.
As a workaround, you can toggle the PLL enable pin after the device is powered-up. This will clear the PLL and force the correct phase delays. Once the PLL re-locks, it will exhibit the correct delay for all settings.
This was fixed in the Quartus II software version 2.2 SP2.