Article ID: 000079501 Content Type: Troubleshooting Last Reviewed: 08/13/2012

Does deasserting pllena (PLL enable) or asserting areset (asynchronous reset) completely disable the VCO in my PLL(s), if I am using either or both of these port in my design?

Environment

  • PLL
  • Reset
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    No.You can use the optional pllena or areset port to disable the PLL output counters, and hence disable the PLL output clock(s). However, deassertion of pllena or assertion of areset will not disable the VCO. These will simply reset the VCO to its nominal value. The only time that the VCO is completely disabled is when you do not have a PLL instantiated in your design.

    For information on how to use and connect pllena and areset in PLL(s), please refer to the respective device handbook or PLL Megafunction users guide.

    Related Products

    This article applies to 1 products

    Stratix® II FPGAs