Article ID: 000080259 Content Type: Product Information & Documentation Last Reviewed: 08/27/2013

How do you implement the altlvds megafunction with the External PLL option in Stratix III devices?



When using the External PLL option in the altlvds megafunction in Stratix® III devices, you can use a left/right PLL setup as a regular PLL and connect the PLL to the altlvds megafunction.

Details of the PLL settings are as follows:

  • Parameter settings:
    • Select left/right PLL type
    • Select feedback path inside the PLL in source-synchronous compensation mode
  • Clk0: High-speed serial clock connected to the rx_inclock or tx_inclock port of the altlvds megafunction
    • Output frequency: Data rate
    • Phase shift: -180 degrees
    • Duty cycle: 50%
  • Clk1: Load-enable signal connected to the rx_enable or tx_enable input port of the altlvds megafunction
    • Output frequency: Data rate/deserialization factor
    • Phase shift: [(deserialization factor – 2)/deserialization factor] * 360 degrees
    • Duty cycle: (100/deserialization factor)%
  • Clk2: Clocks the synchronization register
    • Output frequency: Data rate/deserialization factor
    • Phase shift: (-180/deserialization factor) degrees
    • Duty cycle: 50%
  • If dynamic phase alignment (DPA) is used for the receiver:
    • Refer to the White Paper DPA Circuitry and rx_dpa_locked Signal Behavior in Stratix III Devices (PDF)
    • For Quartus® II 8.0 software or later, select DPA clock on the altpll megafunction. Check “Use these clock settings for DPA clock” in the “Output Clocks” setting tab. This setting should be applied on the output clock which is used as the high speed serial (fast) clock. (See note 1)
    • The Quartus II 7.2 SP3 software and earlier does not have the “Use these clock settings for DPA clock” check box in the altpll megafunction. Set the following in the wrapper file generated for the altpll megafunction: 
      dpa_multiply_by and dpa_divide_by = same multiplication/division factor as Clk0 (i.e., DPA clock frequency is same as data rate).
      • Open the VHDL or Verilog file of the altpll megafunction.
        When you are using Verilog HDL, for example, add the following 2 lines in the defparam section. (Values are dependent to altpll / altlvds setting)
        altpll_component.dpa_multiply_by = <integer>,
        altpll_component.dpa_divide_by = <integer>,
  • This settings works for all deserialization factors and data rates available on the altlvds megafunction.
  • The delay from the data input and LVDS output may be different between altlvds using external PLL and altlvds with internal PLL.

Note 1: If you do not use this setting, the following fitter warning could occur: DPA clock of SERDES receiver atom "rx_0" is driven by PLL "PLL_NAME" with unspecified dpa_multiply_by and dpa_divide_by parameters.

The following fitter error may also occur:
Error: The lvds clock and the DPA clock frequency of SERDES receiver atom "rx_0" must be the same




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