The problem is due to timing model miscorrelation in the Quartus® Prime software version 16.1 and earlier, this affects the Arria® 10 General Purpose Input/Output (GPIO) Double Data rate Input/Output (DDIO) Input path. This miscorrelation causes incorrect timing analysis on the path which leads to timing violation not being captured and reported in the TimeQuest timing analyzer report.
Affected use case are:
- All Arria 10 VID devices that utilize GPIO DDIO Full Rate to Half Rate input path
- All Arria 10 non-VID device (except for 10AX115, 10AX090, 10AT115 and 10AT090) that utilize DDIO Full Rate to Half Rate input path with "io_48_lvds_tile_edge" in the I/O bank used.
For affected design as listed in the use case example above, rerun timing analysis using the Quartus Prime software version 17.0 or later. If timing violations are observed on DDIO_IN Full Rate to Half Rate path, change the phase of the clocks generated from PLL and recompile project