Article ID: 000080419 Content Type: Troubleshooting Last Reviewed: 05/05/2021

Why is an unconstrained clock error reported when using the Error Message Register Unloader Intel® FPGA IP on the Intel® Arria® 10 FPGA?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Error Message Register Unloader Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    An unconstrained clock is reported as shown below when using the Error Message Register Unloader Intel® FPGA IP on the Intel® Arria® 10 FPGA:

    emr_unloader_component|current_state.STATE_CLOCKHIGH

    Resolution

    To work around this problem, generate timing constraints including the command "create_generated_clock" in the SDC file. For example:

    create_generated_clock -name emr_unloader_STATE_CLOCKHIGH -source [get_nets {* |alt_fault_injection_component|alt_fi_inst|twentynm_oscillator}] [get_keepers {* |emr_unloader_component|current_state.STATE_CLOCKHIGH}]

    Related Products

    This article applies to 2 products

    Intel® Cyclone® 10 GX FPGA
    Intel® Arria® 10 FPGAs and SoC FPGAs