Due to a problem in the Quartus® II software release 14.1, some constraints for the Arria® 10 Hard IP for PCI Express® are missing.
Paths to the signal pld_clk_inuse_hip_sync can be set as false paths.
To workaround this issue, add the following constraints to your top level constraint (.sdc) file after any derive_pll_clocks directives:
# HIP testin pins SDC constraints
set_false_path -from [get_pins -compatibility_mode *hip_ctrl*]
set_false_path -from [get_pins -compatibility_mode *altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_rs_a10_hip:g_soft_reset.altpcie_rs_a10_hip|hiprst*]
set_false_path -to [get_registers *altpcie_a10_hip_pipen1b|pld_clk_inuse_hip_sync]
set_false_path -from [get_pins -compatibility_mode *|*reset_status_sync_pldclk_r*]
set_false_path -from [get_registers *altpcie_256_sriov_dma_avmm_hwtcl:apps|altpcierd_hip_rs:rs_hip|app_rstn]
This problem is scheduled to be fixed in a future release of the Quartus II software.
