Why does the SPI SoC Hardware Library (HWLIB) not configure the Control Frame Size?

Description The SoC Hardware Library (HWLIB) can configure and control the SoC Serial Peripheral Interface (SPI) Controllers. The SPI HWLIB source can be found in the /ip/altera/hps/altera_hps/hwlib/src/hwmgr/alt_spi.c file.  The alt_spi.c file contains a function, alt_spi_mw_config_set, that configures the Control Frame Size.  However, this incorrectly uses the ALT_SPIM_CTLR0_DFS_SET define macro.  This causes the Control Frame Size to be written to the Data Frame Size bit field in the control register instead.

Resolution

To work around this issue, replace the "ALT_SPIM_CTLR0_DFS_SET" text within the alt_spi_mw_config_set function in the alt_spi.c file with "ALT_SPIM_CTLR0_CFS_SET".  The updated function should be:

 

//
// Set config parameters to appropriate registers for microwire mode.
//
ALT_STATUS_CODE alt_spi_mw_config_set(ALT_SPI_DEV_t *spi_dev,
                                      const ALT_SPI_MW_CONFIG_t* cfg)
{
    ALT_STATUS_CODE status = ALT_E_SUCCESS;

    if (alt_spi_is_enabled(spi_dev) == ALT_E_TRUE)
    {
        return ALT_E_ERROR;
    }

    if (alt_spi_checking(spi_dev) == ALT_E_FALSE)
    {
        return ALT_E_BAD_ARG;
    }

    if (   cfg->ctl_frame_size > ALT_SPI_MW_CTL_FRAME_SIZE_MAX
        || cfg->mode > ALT_SPI_MW_SEQUENTIAL
        || cfg->dir > ALT_SPI_MW_DIR_TX)
    {
        return ALT_E_ARG_RANGE;
    }

    // Set config parameters to appropriate registers
    uint32_t mwcr_register;
    uint32_t mwcr_mask;
    switch (spi_dev->op_mode)
    {
    case ALT_SPI_OP_MODE_MASTER:
        mwcr_register = ALT_SPIM_MWCR_MWMOD_SET(cfg->mode)
                      | ALT_SPIM_MWCR_MDD_SET(cfg->dir)
                      | ALT_SPIM_MWCR_MHS_SET(cfg->handshake_enabled);

        mwcr_mask     = ALT_SPIM_MWCR_MWMOD_SET_MSK
                      | ALT_SPIM_MWCR_MDD_SET_MSK
                      | ALT_SPIM_MWCR_MHS_SET_MSK;

        alt_replbits_word(ALT_SPIM_MWCR_ADDR(spi_dev->location), mwcr_mask, mwcr_register);
        alt_replbits_word(ALT_SPIM_CTLR0_ADDR(spi_dev->location),
                          ALT_SPIM_CTLR0_CFS_SET_MSK,
                          ALT_SPIM_CTLR0_CFS_SET(cfg->ctl_frame_size));
        break;

    case ALT_SPI_OP_MODE_SLAVE:
        mwcr_register = ALT_SPIS_MWCR_MWMOD_SET(cfg->mode)
                      | ALT_SPIS_MWCR_MDD_SET(cfg->dir);

        mwcr_mask     = ALT_SPIS_MWCR_MWMOD_SET_MSK
                      | ALT_SPIS_MWCR_MDD_SET_MSK;

        alt_replbits_word(ALT_SPIS_MWCR_ADDR(spi_dev->location), mwcr_mask, mwcr_register);
        alt_replbits_word(ALT_SPIS_CTLR0_ADDR(spi_dev->location),
                          ALT_SPIS_CTLR0_CFS_SET_MSK,
                          ALT_SPIS_CTLR0_CFS_SET(cfg->ctl_frame_size));
        break;
    }

    return status;
}

 

This will be fixed in a future version of the Altera SoC Embedded Design Suite.