The Arria® V GZ and Stratix® V Hard IP for PCI Express® may cause third party BFMs to flag invalid symbol after EDS for the following reason:
When the Hard IP for PCI Express enters hot reset, the Link Training Status State Machine(LTSSM) first passes through the Recovery states. When in recovery.idle it starts a data stream, before entering the Hot Reset state, the IP sends EDS to end the Data Stream.
As per the PCI Express specification, the Hard IP should send EIEOS after EDS, but it does not. The Hard IP follows EDS with a TS1 with the hot reset bit set.
This issue can be seen in simulation. No impact has been observed in actual hardware testing.