Article ID: 000086205 Content Type: Troubleshooting Last Reviewed: 12/13/2013

Why does the EDA netlist writer not create a valid netlist for gate-level simulation of the V-Series 28 nm Hard IP for PCI Express MegaCore Function?

Environment

  • Simulation
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description The EDA netlist writer does not currently support gate-level simulation for the V-Series Hard IP for PCI Express® MegaCore® Function.
    Resolution This capability is planned for a future version of the Quartus® II software.

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    This article applies to 13 products

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