When enabling the IPv4 packet type in the eCPRI Intel® FPGA IP, the IPv4 header is inserted due to incorrect register reset values used in the eCPRI Intel FPGA IP.
As a result, you may see the corresponding IPv4 packets are incorrectly routed to the External ST Source Interface instead of the Source Interface of the eCPRI Intel FPGA IP.
To work around this problem in the eCPRI Intel FPGA IP version 21.4 and earlier, follow the steps below.
1. Set bit  to enable IPv4 type in the MAC Packet Type Enable Register.
2. Configure bits [31:28] & bits [27:24] to 0x4 and 0x5 accordingly in the IPv4 Dw0 Register.
3. Configure bits [23:16] to 0x11 accordingly in the IPv4 Dw2 Register.
4. Optional: Configure the remaining RW fields as described in the eCPRI Intel FPGA IP User Guide accordingly based on user’s implementation.
This problem is fixed beginning with has been corrected in the eCPRI web-core IP software version 22.1 release. If you are using a previous version of the eCPRI Intel FPGA IP and notice an issue problems with reading out IPv4 registers, please update the eCPRI web-core IP to the latest software version 22.1 or later.