Article ID: 000090686 Content Type: Errata Last Reviewed: 01/11/2023

Why does the Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example fail timing closure when configured at 25Gbps and Interlaken Look-aside mode is enabled?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interlaken (2nd Generation) Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier the Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example may fail timing closure when configured at 25Gbps and Interlaken Look-aside mode is enabled.

    Resolution

    To work around this problem in the Intel® Quartus® Prime Pro Software version 22.1 and earlier, launch the Design Space Explorer II in the Intel® Quartus® Prime Pro Software and perform seed sweeps.
    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 3 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 GX Signal Integrity Development Kit
    Intel® Stratix® 10 TX Signal Integrity Development Kit