Why does the Intel® Quartus® Prime Pro compilation fail during the Analysis & Synthesis stage when No Development Kit is selected in the F-tile SDI II Intel® FPGA IP Design Example with AXIS-VVP Full enabled?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, the following error message appears during Intel® Quartus® Prime Pro compilation when generating the F-tile SDI II Intel® FPGA IP example design with AXIS-VVP Full enabled and No Development Kit is selected:

• Error(20521): The input refclk of IOPLL axi4s_clk_iopll_inst|axi4s_clk_iopll|tennm_pll is driven by an illegal source: a virtual pin. An IOPLL refclk's source must be either another IOPLL or a dedicated refclk input pin

To work around this problem, when selecting No Development Kit in F-tile SDI II Intel® FPGA IP Design Example with AXIS-VVP Full enabled, comment line <set_instance_assignment -name VIRTUAL_PIN ON -to clk_3a_gpio_p_2> in the Intel® Quartus® Settings File (QSF) file settings and recompile the design. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.