In digital up-conversion, baseband signals are interpolated to intermediate frequency (IF), then digitally modulated by IF sinusoidal carriers. According to the Nyquist theory, the IF carrier frequency is limited to half of the IF circuits sampling frequency. This design example demonstrates how to achieve digital up-conversion with IF carrier frequency that is higher than the Nyquist frequency. The key is to exploit the periodicity of sinusoidal signals and the high sampling frequency of the low voltage differential signal (LVDS) serializer that is embedded on Intel® FPGAs. Modulating IF signals to higher carrier frequencies takes full advantage of the high sampling rate of modern digital-to-analog converters (DAC) and eases the requirement for analog voltage-controlled-oscillators (VCO) and mixers.
Figure 1 shows the block diagram of the polyphase digital up-conversion system. The shaded box contains modules used in this design example. By default, the polyphase filters operate at 100 MHz. With four polyphase components, the output of the LVDS transmitter has a data rate of 400 MHz. In a conventional up-conversion modem, the IF carrier frequency is limited to no more than 50 MHz by the clock frequency of the numerically controlled oscillator (NCO). By exploiting aliasing, however, the output carrier frequency in this design example is centered at 160 MHz.
In Figure 1, inphase and quadrature signals are denoted as I and Q, respectively. Baseband I and Q signals are usually interpolated to a higher data rate using either FIR filter cascade or FIR and CIC filter cascade. The overall upsampling ratio depends on applications and is denoted as a variable 2x in Figure 1.
The polyphase sub-filters are constructed from a low pass filter with a sharp transition band. The coefficients are chosen so that aliased spectrum images can be effectively filtered out by the polyphase FIR filter. Unlike the low pass filter in a conventional up-conversion design, this polyphase filter usually cannot afford to have a wide transition bandwidth.
This example includes a DSP Builder datapath design file and a top-level integration file in VHDL. A testbench and a ModelSim* simulation script are also provided.
Download the Quartus® II software DSP Builder project used in this example:
|Normalized NCO Output Frequency||2/5|
|Real World NCO Output Frequency at 100-MHz Clock||40 MHz|
|Carrier Output Frequency Normalized Over LVDS Output Data Rate||2/5|
|Real World Carrier Output Frequency at 100-MHz Clock||160 MHz|
|Polyphase Filter Input Bit Width||16|
|Polyphase Filter Coefficients Bit Width||18|
|Overall FIR Filter Order||100|
|NCO Accumulator Precision||32|
|NCO Angular Precision||18|
|DAC Bit Width||14|
|LVDS Output Frequency at 100-MHz Input Clock||400 MHz|
|LVDS Transmitter Number of Channels||14|
|LVDS Serialization Factor||4|